A highly specialized field, commonly referred to as "electronic design automation" (EDA), has evolved to handle the demanding and complicated task of designing semiconductor chips. In EDA, computers are extensively used to automate the design process. Computers are ideally suited to performing tasks associated with the design process because computers can be programmed to reduce or decompose large, complicated circuits into a multitude of much simpler functions. Thereupon, the computers can be programmed to iteratively solve these much simpler functions. Indeed, it has now come to the point where the design process has become so overwhelming that the next generation of integrated circuit (IC) chips cannot be designed without the help of computer-aided design (CAD) systems.
And after the circuit for a new semiconductor chip has been designed and physically laid out, there still remains extensive testing which must be performed to verify that this new design and layout works properly. A multitude of different combinations of test vectors are applied as inputs to the design in order to check that the outputs are correct. In the past, many prior art testing and reliability tools assumed a constant voltage source. This approach was deficient because although the design might be functioning perfectly from a logic standpoint, it might, nevertheless, still not meet specifications due to hidden voltage drop problems. In real life, each of the transistors of a semiconductor circuit has an associated voltage drop. This voltage drop is due to the resistance of interconnect wires that connect power supply pads to circuit devices (e.g., transistors) and the current flowing through them. Individually, the voltage drop of a wire attributable to a single transistor is negligible. However, due to rapid advances in semiconductor technology, today's chips can contain upwards of ten million or more transistors. The cumulative effect of all these voltage drops may lead to serious performance degradation or even critical failures. This is especially the case in low-power and high performance designs, whereby the performance as well as functionality of the design are adversely affected by voltage drops (also called IR drop) in the power supply network. If supply voltage level at a device is decreased due to IR drop, the device may not switch at the right time causing malfunction of the chip or it may significantly slow down the speed of the chip.
Moreover, due to the increased resistance of long and narrow interconnect wires in deep submicron(&lt;=0.35 um) VLSI chips, voltage drop in power supply network has become a serious concern to many designers. Accordingly, most high performance IC design companies have added a thorough voltage drop analysis step in their design flow, whereby after physical design(layout) of the chip has been completed, resistors and capacitors from the power network are extracted and backannotated to the original transistor-level netlist to accurately simulate the impact of the voltage drop in the power network on the circuit performance. The "RailMill" tool, available from Synopsys Inc. is the first commercial reliability simulator being used by many IC design companies today that can accurately analyze power network voltage drop of the network.
However, being a transient circuit behavior, accurate analysis of voltage drop in a power network requires dynamic simulation of the circuit based on input vectors. Considering today's large VLSI designs with multi-million transistors, a typical power network is so huge that a single analysis takes from many hours to a few days to complete, depending on the size of the design and the length and accuracy of the simulation.
Thus, there exists a need in the prior art for some method and system which effectively, efficiently, and quickly performs a voltage drop analysis of the power supply network for VLSI designs. The present invention provides one such method and scheme. Basically, the present invention accurately analyzes voltage drops in the power supply network of a VLSI circuit that is much faster than with conventional prior art methods by simulating the power network of the chip only in those instances when there is high switching activity in defined regions of the chip.